Space is a harsh environment due to cosmic radiation and extreme temperature swings. These environmental conditions cause the underlying silicon in processors to degrade in-flight. Over time, this degradation causes a myriad of faults in processors which can lead to program crashes and incorrect results. Fortunately, silicon chips do not fail uniformly, in that certain areas of the chip degrade and fail before the rest of the chip. As a mitigation strategy, reconfiguration in FPGAs offers flexibility where parts of the processor can be moved to another area of the chip to allow for continued safe operation during the mission. These processors and systems-on-chip (SoC) in FPGAs are known as “soft processors”. There are several soft processors that support the RISC-V instruction set architecture (ISA) and are completely open-source in their implementation.

RISC-V has gained popularity as an ISA for space-based processors as it is highly modular through its various extensions, making it easier for designers to tailor the processor for different space applications. Choosing different extensions for a mission profile can reduce power consumption while maintaining the performance and vice-versa. In addition to the modularity, the open-source software systems built for RISC-V make it easier to analyze how faults propagate into system failures across the whole computing stack.

While RISC-V soft processors are of interest for space applications, there are several open-source solutions that have not been benchmarked for these applications. This work analyzes the tradeoffs in performance, power consumption, and resource utilization of open-source soft processors for space applications. Specifically, this work will look at the performance of five processors from the LiteX SoC generator: the Vexriscv, Naxriscv, Rocket, and two configurations of the Vexiiriscv cores. All the selected processors for this work are considered “application class”, meaning that each processor has the necessary hardware structures to support the Linux operating system. Given that each of these processors are highly configurable at the micro-architecture level, certain design constraints are imposed on the base SoC design for all processors in this study. First, L1 cache sizes are set to 8KB with one-way set associativity. L2 caches will be 16KB with one-way set associativity to accommodate the larger L1 cache sizes. All processors, except for the Vexriscv, will be configured for the RV64GC standard. The Vexriscv will be configured for the RV32GC standard. All processors will have a floating point unit to support floating point operations.

This work uses the baremetal applications in the Spacebench suite for analyzing the performance of these soft processors. The Spacebench suite is a collection of applications to test the performance of various computer systems for space applications by measuring the execution time. The applications tested are the multiplication, add, transpose, and convolution matrix operations; Kepler’s equation solver; and the Clohessy–Wiltshire equation solver. For the matrix operations and the Kepler’s equation solver, the applications are executed for each data-type: Int8, Int16, Int32, Single-Precision Floating-Point (SPFP), and Double-Precision Floating-Point (DPFP).