Creating HPSC Supervised Resilient Hardware for Commercial Processors in Space
This program is tentative and subject to change.
Jim Butler serves as Program Manager for NASA’s High Performance Spaceflight Computing (HPSC) project at the Jet Propulsion Laboratory in Pasadena, California. He brings extensive expertise in high-speed semiconductor development, spaceflight computing systems, and digital architecture to critical space technology initiatives
Thomas Lu, Ph.D., Senior Researcher in AI & Data Science at NASA/Jet Proportion Lab. He has been a Principal Investigator and Task Manager for numerous R&D projects spanning AI/ML architecture, algorithms, software and hardware systems. He has investigated multi-core processors, AI accelerators such as GPU/NPU/DSP for fault tolerant space edge-AI computing. He has served as an organizer and a program committee member for SPIE International Conferences, published one book, 2 book chapters, over 70 research papers and presentations in international conferences and journals, 6 patents, over 30 NASA New Technology Reports. He received a Ph.D. degree in Electrical Engineering from the Pennsylvania State University.
This program is tentative and subject to change.
Thu 6 AugDisplayed time zone: Pacific Time (US & Canada) change
13:30 - 15:30 | |||
13:30 35mPanel | Panel 1: Rad-Hard vs. COTS: Can software ever truly fix bad hardware? Resilient AI | ||
14:05 35mPanel | Panel 2: Can LLMs make into Space? Resilient AI Jack Lightholder Jet Propulsion Laboratory, California Institute of Technology, Thomas T. Lu NASA/Caltech/JPL, Scott Tashakkor NASA | ||
14:40 25mTalk | AI: Faults, Architectures, and Resilience Resilient AI | ||
15:05 25mTalk | Creating HPSC Supervised Resilient Hardware for Commercial Processors in Space Resilient AI | ||